1. Field of the Invention
The present invention relates to a complementary heterojunction field effect transistor (CHFET) and a method for making a CHFET, and more particularly, to a CHFET in which the channels for both the p-FET device and the n-FET device forming the complementary structure are formed from either gallium antimonide (GaSb) or indium antimonide (InSb) to provide relatively high electron and hole mobility thereby improving overall performance; the CHFET being formed with common ohmic contacts thereby eliminating the need for separate ohmic contacts for each of the p and n-FET devices to simplify the process for making the CHFET relative to known devices.
2. Description of the Prior Art
Recent trends in advanced communications systems, particularly in satellite communication systems, require lighter weight, smaller size, lower power and lower cost technology. Complementary heterojunction field effect transistors (CHFET) have been shown to be useful for low power and high speed applications. Examples of such CHFETs are disclosed in U.S. Pat. Nos. 5,142,349; 5,192,698; 5,243,206; 5,429,963; 5,479,033; 5,480,829 and 5,544,016.
Such CHFET devices normally include both an n-type FET and a p-type FET formed in a vertically stacked configuration on the same substrate such as gallium arsenide (GaAs). Different materials are known to be used for both the n and p channel layers. For example, in U.S. Pat. No. 5,243,206, gallium antimonide (GaSb) is used for the p-type channel, while indium arsenide (InAs) is used for the n-type channel layer. In U.S. Pat. No. 5,192,698, gallium arsenic antimonide (GaAscSb) is used for the p-type channel layer, while indium gallium arsenide (InGaAs) is used for the p-type channel layer. The particular materials for the p and n-type channel layers are known to be selected, at least in part, to form quantum wells to improve the overall performance of the device. Unfortunately, the performance of such CHFETs is limited by the relatively low mobility of the p-type channel device which limits the speed and increases the overall power consumption of the device.
Another characteristic of such CHEFET devices is that the yield is limited to about 6,000 gate circuits, because of the relative complexity of the fabrication process, known to require about 14 mask levels. Many of the mask levels are due, in part, to separate contacts for both the p and n-type FET devices, for example, as disclosed in U.S. Pat. Nos. 5,192,698; 5,429,963; and 5,479,033.